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femtoclocks? crystal-to-lvds frequency synthesizer ics844008i-01 idt ? / ics ? lvds frequency synthesizer 1 ics844008ayi-01 rev. b november 21, 2008 g eneral d escription the ics844008i-01 is an 8 output lvds synthesizer optimized to generate gbe/10gbe reference clock frequencies and is a member of the hiperclocks tm family of high performance clock solutions from idt. using a 25mhz parallel resonant crystal, the following frequencies can be generated based on the f_sel pin: 125mhz or 156.25mhz. the ics844008i-01 uses idt?s 3 rd generation low phase noise vco technology and can achieve <1ps typical rms phase jitter, easily meeting gbe/10gbe jitter requirements. the ics844008i-01 is packaged in a 32-pin tqfp or 32 vfqfn packages. f eatures ? eight lvds outputs ? crystal oscillator interface ? supports the following output frequencies: 125mhz or 156.25mhz ? vco: 625mhz ? rms phase jitter @ 156.25mhz, using a 25mhz crystal (1.875mhz - 20mhz): 0.38ps (typical) ? full 3.3v supply mode ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) packages hiperclocks? ic s p in a ssignment f requency s elect f unction t able 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 qa0 nqa0 v dd qa1 nqa1 gnd qa2 nqa2 mr nqb0 qb0 gnd v dd nqa3 qa3 f_sel v dda npll_sel v dd oeb gnd xtal_out xtal_in oea ics844008i-01 32-lead tqfp, e-pad 7mm x 7mm x 1.0mm package body y package top view qb3 nqb3 v dd qb2 nqb2 gnd qb1 nqb1 1 0 phase detector vco 625mhz (w/25mhz reference) m = 25 (fixed) 4 5 osc qa0 nqa0 qa1 nqa1 qa2 nqa2 qa3 nqa3 qb0 nqb0 qb1 nqb1 qb2 nqb2 qb3 nqb3 npll_sel xtal_in xtal_out oeb f_sel mr pulldown oea pullup pulldown pullup pullup 25mhz b lock d iagram t u p n i ) z h m ( y c n e u q e r f t u p t u o ) z h m ( y c n e u q e r f t u p n il e s _ fe u l a v r e d i v i d me u l a v r e d i v i d n z h m 5 205 24 5 2 . 6 5 1 z h m 5 215 25 ) t l u a f e d ( 5 2 1 ics844008i-01 32-lead tqfp, e-pad 7mm x 7mm x 1.0mm package body y package top view ics844008i-01 32-lead vfqfn 5mm x 5mm x 0.925mm package body k package top view
idt ? / ics ? lvds frequency synthesizer 2 ics844008ayi-01 rev. b november 21, 2008 ics844008i-01 femtoclocks? crystal-to-lvds frequency synthesizer t able 1. p in d escriptions t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k t able 3a. oea f unction t able t u p n is t u p t u o a e o] 3 : 0 [ a q n , ] 3 : 0 [ a q 0e t a t s e c n a d e p m i h g i h 1n o i t a r e p o l a m r o n t able 3b. oeb f unction t able t u p n is t u p t u o b e o] 3 : 0 [ b q n , ] 3 : 0 [ b q 0e t a t s e c n a d e p m i h g i h 1n o i t a r e p o l a m r o n r e b m u ne m a ne p y tn o i t p i r c s e d 2 , 10 a q n , 0 a qt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d , 2 1 , 3 7 2 , 2 2 v d d r e w o p. s n i p y l p p u s e r o c 5 , 41 a q n , 1 a qt u p u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d , 3 1 , 6 9 2 , 9 1 d n gr e w o p. d n u o r g y l p p u s r e w o p 8 , 72 a q n , 2 a qt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 9l e s _ ft u p n ip u l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . n i p t c e l e s y c n e u q e r f 1 1 , 0 13 a q n , 3 a qt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 5 1 , 4 10 b q n , 0 b qt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 6 1r mt u p n in w o d l l u p e r a s r e d i v i d l a n r e t n i e h t , h g i h c i g o l n e h w . t e s e r r e t s a m h g i h e v i t c a . h g i h o g o t t u p t u o d e t r e v n i e h t d n a w o l o g o t s t u p t u o e u r t e h t g n i s u a c t e s e r . d e l b a n e e r a s t u p t u o e h t d n a s r e d i v i d l a n r e t n i e h t , w o l c i g o l n e h w . s l e v e l e c a f r e t n i l t t v l / s o m c v l 8 1 , 7 11 b q , 1 b q nt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 1 2 , 0 22 b q , 2 b q nt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 4 2 , 3 23 b q , 3 b q nt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 5 2v a d d r e w o p. n i p y l p p u s g o l a n a 6 2l e s _ l l p nt u p n in w o d l l u p , w o l n e h w . s r e d i v i d e h t o t t u p n i s a l a t x d n a l l p e h t n e e w t e b s t c e l e s . ) d e s s a p y b l l p ( l a t x e h t s t c e l e s , h g i h n e h w . ) d e l b a n e l l p ( l l p s t c e l e s . s l e v e l e c a f r e t n i l t t v l / s o m c v l 8 2b e ot u p n ip u l l u p . b 3 e l b a t e e s . s t u p t u o ] 3 : 0 [ b q n / ] 3 : 0 [ b q r o f e l b a n e t u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l 1 3 , 0 3 , t u o _ l a t x n i _ l a t x t u p n i , t u p t u o e h t s i t u o _ l a t x . e c a f r e t n i l a t s y r c t n a n o s e r l e l l a r a p . t u p n i e h t s i n i _ l a t x 2 3a e ot u p n ip u l l u p . a 3 e l b a t e e s . s t u p t u o ] 3 : 0 [ a q n / ] 3 : 0 [ a q r o f e l b a n e t u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l : e t o n n w o d l l u p d n a p u l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r
idt ? / ics ? lvds frequency synthesizer 3 ics844008ayi-01 rev. b november 21, 2008 ics844008i-01 femtoclocks? crystal-to-lvds frequency synthesizer t able 4a. p ower s upply dc c haracteristics , v dd = 3.3v5%, t a = -40c to 85c t able 4b. lvcmos / lvttl dc c haracteristics , v dd = 3.3v5%, t a = -40c to 85c a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o contin uous current 10ma surge current 15ma package thermal impedance, ja 32 tqfp, e-pad 32.2c/w (0 mps) 32 vfqfn 37c/w (0 mps) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional op- eration of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n iv d d v 3 . 3 =2v d d 3 . 0 +v v l i e g a t l o v w o l t u p n iv d d v 3 . 3 =3 . 0 -8 . 0v i h i t u p n i t n e r r u c h g i h l e s _ l l p n , r mv d d v = n i v 5 6 4 . 3 =0 5 1a l e s _ f , b e o , a e ov d d v = n i v 5 6 4 . 3 =5a i l i t u p n i t n e r r u c w o l l e s _ l l p n , r mv d d v , v 5 6 4 . 3 = n i v 0 =5 -a l e s _ f , b e o , a e ov d d v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a t able 4c. lvds dc c haracteristics , v dd = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a d d e g a t l o v y l p p u s g o l a n av d d 0 2 . 0 ?3 . 3v d d v i d d t n e r r u c y l p p u s r e w o p 5 7 2a m i a d d t n e r r u c y l p p u s g o l a n a 0 2a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d o e g a t l o v t u p t u o l a i t n e r e f f i d 5 2 30 5 5v m v d o v d o e g n a h c e d u t i n g a m 0 5v m v s o e g a t l o v t e s f f o2 . 13 . 15 . 1v v s o v s o e g n a h c e d u t i n g a m 0 5v m
idt ? / ics ? lvds frequency synthesizer 4 ics844008ayi-01 rev. b november 21, 2008 ics844008i-01 femtoclocks? crystal-to-lvds frequency synthesizer t able 6. ac c haracteristics , v dd = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 0 = l e s f5 2 . 6 5 1z h m 1 = l e s f5 2 1z h m t ) o ( k s2 , 1 e t o n ; w e k s t u p t u o 0 1 1s p t ) c c ( t i jr e t t i j e l c y c - o t - e l c y c 5 2s p t ) ? ( t i j ; ) m o d n a r ( r e t t i j e s a h p s m r 3 e t o n ) z h m 0 2 - z h m 5 7 8 . 1 ( , z h m 5 2 18 3 . 0s p ) z h m 0 2 - z h m 5 7 8 . 1 ( , z h m 5 2 . 6 5 12 4 . 0s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 30 0 7s p c d oe l c y c y t u d t u p t u o 7 43 5% d e h s i l b a t s e s i h c i h w , e g n a r e r u t a r e p m e t g n i t a r e p o t n e i b m a d e i f i c e p s e h t r e v o d e e t n a r a u g e r a s r e t e m a r a p l a c i r t c e l e : e t o n t e e m l l i w e c i v e d e h t . m p f l 0 0 5 n a h t r e t a e r g w o l f r i a e s r e v s n a r t d e n i a t n i a m h t i w t e k c o s t s e t a n i d e t n u o m s i e c i v e d e h t n e h w . s n o t i d n o c e s e h t r e d n u d e h c a e r n e e b s a h m u i r b i l i u q e l a m r e h t r e t f a s n o i t a c i f i c e p s . s n o i t i d n o c d a o l l a u q e h t i w d n a s e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 1 e t o n . s t n i o p s s o r c l a i t n e r e f f i d e h t t a d e r u s a e m . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 2 e t o n . t o l p e s i o n e s a h p e h t o t r e f e r e s a e l p : 3 e t o n t able 5. c rystal c haracteristics r e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n o i t a l l i c s o f o e d o m l a t n e m a d n u f y c n e u q e r f 5 2z h m ) r s e ( e c n a t s i s e r s e i r e s t n e l a v i u q e 0 5 e c n a t i c a p a c t n u h s 5f p . l a t s y r c t n a n o s e r l e l l a r a p f p 8 1 n a g n i s u d e z i r e t c a r a h c : e t o n
idt ? / ics ? lvds frequency synthesizer 5 ics844008ayi-01 rev. b november 21, 2008 ics844008i-01 femtoclocks? crystal-to-lvds frequency synthesizer t ypical p hase n oise at 125mh z 125mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.38ps (typical) o ffset f requency (h z ) dbc hz n oise p ower ? ? raw phase noise data t ypical p hase n oise at 156.25mh z 156.25mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.42ps (typical) o ffset f requency (h z ) dbc hz n oise p ower ? ? raw phase noise data ? ? gigabit ethernet filter phase noise result by adding a gigabit ethernet filter to raw data phase noise result by adding a gigabit ethernet filter to raw data gigabit ethernet filter
idt ? / ics ? lvds frequency synthesizer 6 ics844008ayi-01 rev. b november 21, 2008 ics844008i-01 femtoclocks? crystal-to-lvds frequency synthesizer p arameter m easurement i nformation rms p hase j itter 3.3v c ore /3.3v o utput l oad ac t est c ircuit t sk(o) qy qx nqy nqx phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power t pw t period t pw t period odc = x 100% c ycle - to -c ycle j itter o utput s kew scope qx nqx 3.3v5% power supply +? float gnd lvds o utput r ise /f all t ime o utput d uty c ycle /p ulse w idth /p eriod t cycle n t cycle n+1 t jit(cc) = t cycle n ? t cycle n+1 1000 cycles nqa0:nqa3, nqb0:nqb3 20% 80% 80% 20% t r t f v od v dda v dd qa0:qa3, qb0:qb3 nqa0:nqa3, nqb0:nqb3 qa0:qa3, qb0:qb3 nqa0:nqa3, nqb0:nqb3 qa0:qa3, qb0:qb3 d ifferential o utput v oltage s etup o ffset v oltage s etup out out lvds dc input v os / v os v dd 100 out out lv d s dc input v od / v od v dd
idt ? / ics ? lvds frequency synthesizer 7 ics844008ayi-01 rev. b november 21, 2008 ics844008i-01 femtoclocks? crystal-to-lvds frequency synthesizer a pplication i nformation as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter perfor- mance, power supply isolation is required. the i cs844008i-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd and v dda should be individually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. figure 1 illustrates this for a generic v dd pin and also shows that v dda requires that an additional10 resistor along with a 10f bypass capacitor be connected to the v dda pin. p ower s upply f iltering t echniques f igure 1. p ower s upply f iltering 10 v dda 10 f .01 f 3.3v .01 f v dd i nputs : lvcmos c ontrol p ins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvds o utputs all unused lvds outputs should be terminated with 100 resistor between the differential pair.
idt ? / ics ? lvds frequency synthesizer 8 ics844008ayi-01 rev. b november 21, 2008 ics844008i-01 femtoclocks? crystal-to-lvds frequency synthesizer lvcmos to xtal i nterface the xtal_in input can accept a single-ended lvcmos signal through an ac couple capacitor. a general interface diagram is shown in figure 3. the xtal_out pin can be left floating. the input edge rate can be as slow as 10ns. for lvcmos inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. this configuration requires that the output impedance of the driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 applications, r1 and r2 can be 100 . this can also be accomplished by removing r1 and making r2 50 . f igure 3. g eneral d iagram for lvcmos d river to xtal i nput i nterface xta l _ i n xta l _ o u t vcc r2 ro r1 zo = 50 rs vcc .1uf v dd v dd zo = ro + rs c rystal i nput i nterface the ics844008i-01 has been characterized with an 18pf parallel resonant crystals. the capacitor values shown in f igure 2. c rystal i npu t i nterface figure 2 below were determined using a 25mhz parallel resonant crystal and were chosen to minimize the ppm error. xtal_in xtal_out x1 18pf parallel crystal c1 27p c2 27p
idt ? / ics ? lvds frequency synthesizer 9 ics844008ayi-01 rev. b november 21, 2008 ics844008i-01 femtoclocks? crystal-to-lvds frequency synthesizer f igure 5. a ssembly for e xposed p ad t hermal r elease p ath ?s ide v iew (d rawing not to s cale ) epad t hermal r elease p ath in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 5. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. ground plane land pattern solder thermal via exposed heat slug (ground pad) pin pin pad solder pin pin pad solder f igure 4. t ypical lvds d river t ermination 3.3v lvds d river t ermination a general lvds interface is shown in figure 4. in a 100 differential transmission line environment, lvds drivers require a matched load termination of 100 across near the receiver input. for a multiple lvds outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. r1 100 3.3v 100 ohm differential transmission line 3.3v + - lvds
idt ? / ics ? lvds frequency synthesizer 10 ics844008ayi-01 rev. b november 21, 2008 ics844008i-01 femtoclocks? crystal-to-lvds frequency synthesizer f igure 6. p.c.a ssembly for e xposed p ad t hermal r elease p ath ?s ide v iew (d rawing not to s cale ) vfqfn epad t hermal r elease p ath in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 6. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. thermal via land pattern solder pin solder pin pad pin pad pin ground plane exposed heat slug (ground pad)
idt ? / ics ? lvds frequency synthesizer 11 ics844008ayi-01 rev. b november 21, 2008 ics844008i-01 femtoclocks? crystal-to-lvds frequency synthesizer vdd q7 vdd qa2 vdd=3.3v nqb2 mr c5 0.1uf qa0 qb1 r1 10 zo = 50 ohm qa3 rd1 not install oea logic control input examples vdd ru2 not install nq5 vdd c6 0.1uf set logic input to '0' to logic input pins nqa3 f_sel r4 50 c9 0.1uf c8 0.1uf c1 27pf vdd nqa0 vdd nqb0 + - nq7 nqb1 c4 10uf nqa1 zo = 50 ohm to logic input pins nqa2 + - vdd qa1 vdda nqb3 npll_sel c7 0.1uf qb2 set logic input to '1' r3 50 zo = 50 ohm rd2 1k c3 0.01u ru1 1k oeb u1 ics844008i-01 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 qa0 nqa0 vdd qa1 nqa1 gnd qa2 nqa2 f_sel qa3 nqa3 vdd gnd qb0 nqb0 mr nqb1 qb1 gnd nqb2 qb2 vdd nqb3 qb3 oea xtal_in xtal_out gnd oeb vdd npll_sel vdda 1 8 p f qb3 q5 r2 100 alternate lvds termination qb0 zo = 50 ohm x1 25mhz c2 27pf s chematic l ayout figure 7 shows an example of ics844008i-01 application schematic. in this example, the device is operated at v dd = 3.3v. the 18pf parallel resonant 25mhz crystal is used. the c1 = 27pf and c2 = 27pf are recommended for frequency accuracy. f igure 7. ics844008i-01 s chematic l ayout for different board layout, the c1 and c2 may be slightly adjusted for optimizing frequency accuracy. two examples of lvds for receiver without built-in termination are shown in this schematic.
idt ? / ics ? lvds frequency synthesizer 12 ics844008ayi-01 rev. b november 21, 2008 ics844008i-01 femtoclocks? crystal-to-lvds frequency synthesizer p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics844008i-01. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics844008i-01 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. ? power (core) max = v dd_max * (i dd_max + i dda_max ) = 3.465v * (275ma + 20ma) = 1022.175mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 37c/w per table 7b below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 1.022w * 37c/w = 122.8c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (multi-layer). t able 7a. t hermal r esistance ja for 32-l ead tqfp, e-p ad f orced c onvection ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 32.2c/w 26.3c/w 24.7c/w t able 7b. t hermal r esistance ja for 32-l ead vfqfn, f orced c onvection ja vs. air flow (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 37.0c/w 32.4c/w 29.0c/w
idt ? / ics ? lvds frequency synthesizer 13 ics844008ayi-01 rev. b november 21, 2008 ics844008i-01 femtoclocks? crystal-to-lvds frequency synthesizer r eliability i nformation t ransistor c ount the transistor count for ics844008i-01 is: 2652 t able 8a. ja vs . a ir f low t able for 32 l ead tqfp, e-p ad ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 32.2c/w 26.3c/w 24.7c/w t able 8b. ja vs . a ir f low t able for 32 l ead vfqfn ja vs. air flow (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 37.0c/w 32.4c/w 29.0c/w
idt ? / ics ? lvds frequency synthesizer 14 ics844008ayi-01 rev. b november 21, 2008 ics844008i-01 femtoclocks? crystal-to-lvds frequency synthesizer p ackage o utline - y s uffix for 32 l ead tqfp, e-p ad t able 9a. p ackage d imensions reference document: jedec publication 95, ms-026 -hd version exposed pad down n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s d h - a b a m u m i n i ml a n i m o nm u m i x a m n 2 3 a - -- -0 2 . 1 1 a 5 0 . 00 1 . 05 1 . 0 2 a 5 9 . 00 . 15 0 . 1 b 0 3 . 05 3 . 00 4 . 0 c 9 0 . 0- -0 2 . 0 d c i s a b 0 0 . 9 1 d c i s a b 0 0 . 7 2 d . f e r 0 6 . 5 e c i s a b 0 0 . 9 1 e c i s a b 0 0 . 7 2 e . f e r 0 6 . 5 e c i s a b 0 8 . 0 l 5 4 . 00 6 . 05 7 . 0 0 - - 7 c c c - -- -0 1 . 0 3 d & 3 d 0 . 35 . 30 . 4
idt ? / ics ? lvds frequency synthesizer 15 ics844008ayi-01 rev. b november 21, 2008 ics844008i-01 femtoclocks? crystal-to-lvds frequency synthesizer p ackage o utline - k s uffix for 32 l ead vfqfn t able 9b. p ackage d imensions reference document: jedec publication 95, mo-220 note: the following package mechanical drawing is a generic drawing that applies to any pin count vfqfn package. this draw- ing is not intended to convey the actual pin count or pin layout of this device. the pin count and pinout are shown on the front page. the package dimensions are in table 9 below. n o i t a i r a v c e d e j ) 4 - / 2 - d h h v ( s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y sm u m i n i mm u m i x a m n 2 3 a 0 8 . 00 . 1 1 a 05 0 . 0 3 a e c n e r e f e r 5 2 . 0 b 8 1 . 00 3 . 0 e c i s a b 0 5 . 0 n d 8 n e 8 e , d c i s a b 0 . 5 2 e , 2 d 0 . 33 . 3 l 0 3 . 00 5 . 0
idt ? / ics ? lvds frequency synthesizer 16 ics844008ayi-01 rev. b november 21, 2008 ics844008i-01 femtoclocks? crystal-to-lvds frequency synthesizer while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extraordinary environmental r equirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. t able 10. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t f l 1 0 - i y a 8 0 0 4 4 8l 1 0 i a 8 0 0 4 s c id a p - e , p f q t " e e r f - d a e l " d a e l 2 3e b u tc 5 8 o t c 0 4 - t f l 1 0 - i y a 8 0 0 4 4 8l 1 0 i a 8 0 0 4 s c id a p - e , p f q t " e e r f - d a e l " d a e l 2 3l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - f l 1 0 - i k a 8 0 0 4 4 8l 1 0 i a 8 0 0 s c in f q f v " e e r f - d a e l " d a e l 2 3y a r tc 5 8 o t c 0 4 - f l 1 0 - i k a 8 0 0 4 4 8l 1 0 i a 8 0 0 s c in f q f v " e e r f - d a e l " d a e l 2 3l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
idt ? / ics ? lvds frequency synthesizer 17 ics844008ayi-01 rev. b november 21, 2008 ics844008i-01 femtoclocks? crystal-to-lvds frequency synthesizer t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d b 6 t4 o t m u m i m x a m s p 5 7 m o r f t i m i l r e t t i j e l c y c - o t - e l c y c d e t c e r r o c - e l b a t s c i t s i r e t c a r a h c c a . m u m i x a m s p 5 2 8 0 / 3 1 / 5 b 0 1. t u o y a l c i t a m e h c s d e d d a . t e e h s a t a d e h t t u o h g u o r h t e g a k c a p n f q f v 2 3 d e d d a 8 0 / 1 2 / 1 1
ics844008i-01 femtoclocks? crystal-to-lvds frequency synthesizer innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt for tech support netcom@idt.com +480-763-2056 corporate headquarters integrated device t echnology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800-345-7015 (inside usa) +408-284-8200 (outside usa) ? 2008 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa

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